VLSI Design - 45 Days Internship Training Program
Join 45 Days VLSI Design Internship Training Program at NextVision Infotech. Learn Verilog, RTL, verification, synthesis, FPGA. ₹649 only with certificate.
Program Description
Skills You'll Learn
Projects You'll Work On
Complete VLSI Design Project
Students will complete a full VLSI design project including RTL design using Verilog, testbench creation, functional verification, synthesis, timing analysis, FPGA implementation, and complete project documentation as per industry standards.
Program Modules
W1: Week 1: VLSI Fundamentals and Digital Electronics
Introduction to VLSI, VLSI design flow, Moore law, scaling, ASIC vs FPGA, full custom, semi-custom, standard cell, gate array, digital electronics fundamentals, number systems, Boolean algebra, logic gates, combinational logic, sequential logic, latches, flip-flops, SR flip-flop, JK flip-flop, D flip-flop, T flip-flop, registers, counters, shift registers, memory - RAM, ROM, SRAM, DRAM, CMOS technology, NMOS, PMOS, CMOS inverter, CMOS logic gates, transmission gates, pass transistor logic, dynamic logic, power dissipation, low power design.
W2: Week 2: Verilog HDL
Introduction to Verilog HDL, Verilog vs VHDL, module structure, ports, data types - wire, reg, integer, real, time, parameters, operators, continuous assignment, procedural blocks - always, initial, blocking vs non-blocking assignments, conditional statements, case statements, loops, tasks, functions, system tasks, compiler directives, timing controls, delay modeling, gate-level modeling, dataflow modeling, behavioral modeling, structural modeling, module instantiation, port connections, hierarchical design.
W3: Week 3: Combinational and Sequential Circuit Design
Combinational circuit design - adders, half adder, full adder, ripple carry adder, carry look ahead adder, subtractors, multipliers, multiplexers, demultiplexers, encoders, decoders, comparators, parity generators, code converters, sequential circuit design - latches, flip-flops, registers, shift registers, counters, synchronous counters, asynchronous counters, ring counters, Johnson counters, up-down counters, modulo counters, clock dividers, frequency dividers, memory design - RAM, ROM, FIFO, LIFO.
W4: Week 4: FSM and RTL Design
Finite state machine (FSM), Moore machine, Mealy machine, state diagrams, state tables, state encoding, binary encoding, gray encoding, one-hot encoding, FSM design, sequence detector, traffic light controller, vending machine, elevator controller, UART, SPI, I2C, RTL design, register transfer level, data path design, control path design, ASM charts, algorithmic state machine, pipelining, retiming, RTL coding guidelines, synthesis-friendly coding.
W5: Week 5: Verification, Synthesis, FPGA, and Live Projects
Verification fundamentals, testbench creation, stimulus generation, response checking, self-checking testbench, directed testing, random testing, functional coverage, code coverage, assertion-based verification, SystemVerilog basics, UVM overview, synthesis, synthesis flow, synthesis tools - Xilinx Vivado, Cadence Genus, Synopsys Design Compiler, synthesis constraints, timing analysis, static timing analysis (STA), setup time, hold time, clock skew, clock tree synthesis, FPGA architecture, FPGA design flow, FPGA implementation, bitstream generation, FPGA boards - Xilinx, Altera, Lattice, live projects - ALU, UART, SPI, I2C, FIFO, traffic light controller, complete documentation.
W6: Week 6: Documentation, Viva, and Certification
Project documentation, RTL documentation, testbench documentation, verification report, synthesis report, timing report, FPGA implementation report, project report preparation, resume building, interview preparation, viva-voce examination, feedback session, certificate distribution.
Key Features
What You'll Learn
Examination Details
| Exam Name | Full Marks | Pass Marks |
|---|---|---|
| Module-wise Assessment | 100 | 40 |
| Project Evaluation | 100 | 50 |
| Final Presentation | 50 | 25 |
| Viva-Voce | 50 | 25 |
Internship Details
Prerequisites
- Pursuing or completed B.Tech/B.E./Diploma in Electronics, ECE, EEE, or related field
- Basic knowledge of digital electronics
- Basic knowledge of programming
- Interest in VLSI design
Who Can Enroll ?
- B.Tech ECE students (1st to 8th semester)
- B.E. ECE students
- B.Tech Electronics Engineering students
- B.Tech Electrical Engineering students
- Diploma Electronics students (1st to 6th semester)
- Polytechnic students
- Working professionals wanting to upskill
- Students from all over India seeking practical training
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